ASIC Engineer – SDC: High Salary, Growth, and Leading-Edge SoC Development

Discover the ASIC Engineer SDC offer: high salary, bonus, top benefits, technical growth, and impact on next-gen SoC. See pros, cons, and if it's your next big move!

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Ingeniero de ASIC – SDC

Lead timing constraint development for high-end SoCs. Compelling salary and benefits. Onsite, growth-focused, with significant impact on digital infrastructure.




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The ASIC Engineer – SDC opportunity comes with an attractive salary range from $165,000 to $241,400 USD, reflecting high market demand and value for expertise. The role is onsite, offering full-time employment, comprehensive healthcare, 401(k) matching, paid time off, and bonus eligibility, ensuring a robust package for top engineering talent.

What Does the Day-to-Day Look Like?

In this position, you’ll own the development of full-chip timing constraints (SDC) for advanced networking SoCs. Driving Static Timing Analysis (STA) is a core part of your remit.

Expect deep, proactive collaboration with RTL, physical design, and DFT teams to resolve complex timing issues. You’ll guide timing-driven design improvements for optimal performance and manufacturability.

You will define and maintain clocking architectures while validating the integration of third-party IP constraints into the full system-on-chip environment.

Responsibility extends to developing, reviewing, and aligning block-level SDCs, ensuring each constraint meets rigorous correctness requirements across design hierarchies.

Supporting the silicon through timing closure and readiness for multiple operational modes and conditions is essential for ensuring quality and delivery.

Pros: Growth and Impact

This role grants you the chance to influence major networking technologies, connecting millions of people and enterprises globally.

With a team-oriented environment and access to world-class resources, training, and collaboration, you’ll maximize your career trajectory while working on leading-edge silicon processes.

Cons: Requirements and Commitments

The rigorous onsite requirement of four days per week can limit flexibility, especially for those accustomed to remote or hybrid work arrangements.

Complex hardware environments and cutting-edge technologies demand continuous learning, potentially increasing the pressure and expectations to remain ahead of the curve.

Veredicto final

The ASIC Engineer – SDC position is well-suited for ambitious professionals ready to step up and make a visible impact. If you thrive on technical challenges, cross-functional teamwork, and want rewards commensurate to your expertise, this opportunity is compelling and highly recommended.

Recomendado para ti

Ingeniero de ASIC – SDC

Lead timing constraint development for high-end SoCs. Compelling salary and benefits. Onsite, growth-focused, with significant impact on digital infrastructure.




Serás redirigido a otro sitio web.

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